RFIC Packaging Design Manager
San Diego , California , United States
Posted: Oct 1, 2021
Role Number: 200295155
Do you love working on challenges that no one has solved yet? Do you like changing the game? Envision what you could do here! At Apple, we believe new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Apple is seeking an experienced RFIC package design manger to support RF and 5G products. In this highly visible role, you will participate in advanced package/SIP selection, and configuration optimization. You will be responsible for package/SIP layout, performance optimization, design verification and tape out.
- We are looking for someone ideally with 8+years work experience in RF packaging design area, familiar with package design tools such as Cadence APD/SIP; Cadence Concept HDL for schematic review, experience in schematic capture and system integration.
- Ideal candidate will have good understanding in micro-electronic package structure, mechanical, electrical and thermal performance. Familiar with various package type and understand trade-offs, constraints, have design experience of RFIC and 5G packages and modules.
- Able to work with design teams to translate IC/system requirement into package/SIP configuration.
- Knowledge of signal and power integrity, familiar with SIPI tools (HFSS, XIM). Knowledge of high-speed layout constraints (Crosstalk mitigation, differential pairs, EMI/RFI, PCB/Package resonance).
- Strong knowledge of Design Rules Check (DRC) and Design for Manufacturing (DFM); Familiar with layout/artwork review tools such as CAM350/Valor.
As a packaging design lead/manager, your responsibility is to lead the team providing package solutions for Apple wireless and cellular chips. Define package type, conduct feasibility study and implement the physical layout; Work with cross-functional teams including platform architecture, PD, SOC design, system, SIPI, assembly and technology to understand system requirements and physical design limitations; Drive co-optimization of silicon floor plan, bump placement and package pin out. Make sure the layout meets signal/power integrity requirement. Drive methodology, innovations, and productivity improvements in package/SIP design together with vendors and developers on feature development and bug resolution.
Education & Experience
Bachelors required. MS or higher degree preferred.