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 Power Integrity Engineer - Austin, Texas, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Platforms
Computers - Networks
Computers - Software Engineer
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200295460 / Latpro-3829479 
Date posted: Oct-05-2021
State, Zip: Texas, 78729


Power Integrity Engineer

Austin , Texas , United States



Posted: Oct 4, 2021

Weekly Hours: 40

Role Number: 200295460

The Mac organization is looking for an outstanding engineer to support the system-level Power Distribution Network (PDN) design, analysis and validation aspects of Mac and Accessory products development. You should have deep knowledge and familiarity with power delivery network design, analysis and validation methods. You will work with multi-functional teams design and implement a power supply network solution, develop and validate impedance and droop targets and verify the quality of the power supply using lab and in-situ silicon measurements.

Key Qualifications

  • You must have proven technical understanding of power supply architectures covering voltage regulator technologies, power distribution network (PDN) modeling, PCB design practices and trade-offs for PDN design and optimization.
  • You should have a good understanding of multi-phase of Buck/Boost converter and LDO design principles, operating modes, and system integration careabouts.
  • Solid understanding in 3D/2D EM simulation tools, electromagnetic modeling and transmission line theory is required.
  • Skills with associated tools for 2.5D (PowerSI, SIWave, Sentinel-PI, nSys), 3D Full wave (HFSS, nWave), quasi-static tools (Q3D, nApex) is required.
  • Relevant proven understanding of HSPICE, Spectre, AMS, and Simplis models for system-level transient droop analysis is also necessary.
  • Deep Experience in CPM (Chip-Power-Model) usage for system transient analysis is an added benefit.
  • In this role, you will be expected to have understanding of die-package-board power delivery network co-design constraints and tradeoffs.


This exciting role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. Ability to execute on target impedance analysis, transient voltage droop and phase margin/stability analysis is required. The candidate is also expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. The candidates is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. The role includes the PI support through the specific project design process which can include system pathfinding and verification stages, and characterization reviews with continuing mentorship through production and ramp.

Education & Experience

M.S. with 5-7 years experience, or PhD (preferred) with minimum of 3-4 years experience

Additional Requirements

  • Experience with Perl, Python or other scripting languages is desired. MatLab Experience is a plus
  • Excellent documentation and interpersonal skills, ability to work independently, a desire to mentor, and demonstrated ability to innovate are required.
  • Candidate is also expected to have proven experience in driving initiatives that improved process, procedures, and result quality.


See job description


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