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 SerDes Validation Architect - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Platforms
Computers - Networks
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200295483 / Latpro-3829480 
Date posted: Oct-05-2021
State, Zip: California, 95014

Description

SerDes Validation Architect

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Oct 4, 2021

Weekly Hours: 40

Role Number: 200295483

The candidate will work within the Mac Hardware organization in the area of analysis and validation methodology development for High Speed Serial Interfaces . This will include design simulation, enabling in situ system design performance metrics capture, enabling external I/O compliance and factory level eye-scan test flow development, system compliance flow development, analysis automation of SI, data set metrics, correlation closure between simulation and performance metrics.

Key Qualifications

  • You must have familiarity and proven expertise in SI simulation process for serdes links including Spice, AMI, statistical methods and demonstrated ability to automate such process steps to include leverage of commercial solvers for Signal Integrity studies of SerDes interfaces as applicable.
  • Familiarity with processing S-parameters and transform methods from frequency domain to time domain step responses is required.
  • Fluent understanding of interconnect modeling methods, using S-parameter, W-elements, etc is required.
  • Key skills required include ability to execute and author code to support DoE analysis of candidate designs and hardware variants.
  • The candidate should be familiar with High Speed SerDes compliance process for standard interfaces (CIO40, USB3, DP, PCIe, LPDP) and be adept at automation process for end-to-end system-level PHY compliance closure, leading partnership with Apple SW/FW teams, PHY/Controller teams and instrumentation vendors in the process.
  • The candidate shall have demonstrated skill and working knowledge in scripting, programming expertise in C, C++, Python, PERL, and BASH/CSH; Git; Windows/Linux/Unix; SKILL (cadence) and Matlab.
  • Demonstrated abilities in OO programming, inheritance, polymorphism, data-typing; multi-dim arrays, dictionaries; regular expressions is required.
  • Experience with batch (non-GUI) processing support of the analysis suite is required.
  • The candidate is expected to have a deep understanding and working knowledge of SerDes IPs and its functional blocks, as well experience of register programming for configuring SerDes PHY and Controller blocks for system integration and validation needs.
  • This also includes ability to develop scripts to engage with and use on-chip diagnostic capabilities for testing SI metrics at scale on high speed serial interfaces.
  • Ability to contribute in a team setting.
  • Excellent documentation and communication skills, ability to work independently, a desire to mentor, and demonstrated ability to innovate are required.

Description

The position includes design and analysis in electrical system development process across signaling and power domains. The roll includes automation of analysis and design in system SI and PI efforts across the full range of the product development process. Teamwork includes coordination with peers, system design SI/PI, hardware validation, and project EE engineering teams.

Education & Experience

MSEE or PhD, 10 years experience in system or device design and analysis.



Requirements

See job description

 

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