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 SOC Performance Validation Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Platforms
Computers - Networks
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200297283 / Latpro-3831661 
Date posted: Oct-13-2021
State, Zip: California, 95014

Description

SOC Performance Validation Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Oct 12, 2021

Role Number: 200297283

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! In this role, you will be a member of the Platform Architecture team, working within the hardware technology group to shape the architecture of Apple's future System-on-Chips (SoC). We are seeking an upbeat and highly motivated SOC performance engineer to drive the architectural validation and design correlation of our software-based performance model.

Key Qualifications

  • MINIMUM QUALIFICATIONS:
  • Knowledge of computer architecture
  • Practical experience with data structures and algorithms
  • Understanding of software engineering principles
  • Solid programming skills in C, C++ or equivalent languages
  • Experience with scripting languages like Python, Perl, Lua, Bash
  • Ability to study a problem in depth, design experiments, analyze data, and present results
  • PREFERRED QUALIFICATIONS:
  • Significant architectural research or embedded systems projects
  • Experience with micro-architectural performance modeling and architectural exploration
  • Experience with architectural, micro-architectural validation and performance correlation
  • Experience with on-chip interconnect fabrics, caches, and memory/DRAM controllers, quality-of-service architecture

Description

You will help define the comprehensive performance test plan, systematic test methodology, and develop novel infrastructure for the software simulator for iPhone/iPad/Mac/Watch SoCs. The team pushes the system to its limits to help find and fix architectural and micro-architectural issues. Your data shall contribute to product performance and power trade-off decisions in our SoCs. This role will be highly visible and critical for driving architecture improvements in Apple's future products. YOUR RESPONSIBILITIES WILL INCLUDE: - Learning about the state of the art in SoC IP and chip-level architecture - Defining test plans and test planning methodology - Definition and implementation of validation infrastructure like performance monitors, behavioral checkers, state space coverage - Working on data analysis pipelines, visualization methodologies, continuous regression testing - Running performance simulation of future applications - Careful analysis and presentation of simulation results - Tuning and validating future SoC HW/SW for the best user experience - Interface and collaboration with cross-functional teams: architecture, hardware and software teams for collaborative debug, and correlation studies

Education & Experience

- BS or MS or PhD in CS, EE, or related field



Requirements

See job description

 

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