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 RF PLL Design Engineer - Irvine, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Platforms
Computers - Software Engineer
Computers - Webmaster
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200307914 / Latpro-3840354 
Date posted: Nov-12-2021
State, Zip: California, 92602


RF PLL Design Engineer

Irvine , California , United States



Posted: Nov 11, 2021

Role Number: 200307914

The wireless RFIC team architects, designs, and validates radio transceivers integrated into complex wireless SoCs. Our transceivers have powered wireless connectivity solutions for Apple wearable products, enabling the smallest form factor at the lowest power envelope. You will have the opportunity to do innovative development in transceiver design while working closely with systems and product teams at Apple. In this highly visible role, you will drive innovation within a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly. You will utilize your virtuoso knowledge to design PLL Circuits and component blocks, and other RF/mixed-signal blocks. You will also apply your technical analysis skills to do feasibility studies at transistor-level for new RF circuit architectures, as well as be responsible for simulation and modeling to design and develop analog and mixed signal solutions for next generation wireless chips. Would you like to join us and do the work of your life here?

Key Qualifications

  • We want you to have
  • 5+ years of experience in RF/analog / high-speed digital design in advanced CMOS process nodes.
  • Extensive experience with designing fractional-N PLLs, sigma-delta PLLs, and VCOs.
  • Strong knowledge of loop design to optimize for phase noise/jitter, lock time, reference spur, area, power, etc.
  • Experienced in designing ADPLLs, TDC, DTC, Digital Loop Filters, and DCOs. Modeling, analysis and design of SD noise cancellation and spur cancellation techniques.
  • Knowledge of bandgaps, bias, opamps, LDOs, feedback, and compensation techniques.
  • Familiarity with Cadence Virtuoso, SpectreRF, and/or C/Matlab/VerilogA modeling.
  • Familiarity with various RF transceiver architectures and their trade-offs is considered a plus.


As a RF PLL design engineer, you will be providing RF/analog/mixed-signal solutions for wireless chips. - Design analog PLLs, PFD, Charge-Pump, Loop Filter, VCO, MMD, LO generation, Dividers, XTAL, and etc. - Design All Digital PLLs, TDC, DTC, Digital Loop Filter, DCO, MMD, digital calibration and noise / spur cancellation. - Conduct transistor-level feasibility studies for new RF circuit architectures and collaborating with platform architects and systems groups to define overall PLL specs. - Work on behavioral modeling of PLL / ADPLL to derive block-level requirements. - Floorplan and work with layout designers to implement circuit design with best-practice layout techniques. - Define bench-level test plans and validating, characterizing, and debugging designs through mass production.

Education & Experience

BSEE required, MSEE/PhD preferred.

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.


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