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 Neural Engine HW Modeling Architect - Platform Architecture - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Platforms
Computers - Networks
Computers - Software Engineer
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200314567 / Latpro-3841592 
Date posted: Nov-17-2021
State, Zip: California, 95014


Neural Engine HW Modeling Architect - Platform Architecture

Santa Clara Valley (Cupertino) , California , United States



Posted: Nov 16, 2021

Role Number: 200314567

Do you love crafting elegant solutions to highly complex challenges? Are you a big-picture visionary who understands how each element affects all the others? At Apple, our Architecture group is responsible for connecting our hardware and software into one unified system. You'll collaborate with engineers across Apple to design how all of our technologies work in unison, drive development of our renowned system-on-a-chip architecture. Develop algorithms for platform power, performance, and thermal management, and develop forward-looking prototype systems as well as build and deploy software development tools that will be distributed to the Apple engineering community. Join this team and help build the seamless technology experiences we're known for worldwide! The Platform Architecture team is looking for a Neural Engine HW Modeling Architect who will work on performance modeling and/or compiler prototyping for the next-generation Neural Engine HW architecture.

Key Qualifications

  • Excellent programming skills in C++ and Python.
  • Solid understanding of DNN acceleration architectures and their key performance tradeoffs.
  • Familiarity with state-of-the-art DNN workloads and their compute and memory requirements.
  • Ability to write performance models of HW accelerators using transaction and cycle-level abstractions.
  • Ability to prototype software frameworks (such as compilers) for mapping DNN workloads to HW accelerators.
  • Familiarity with digital design and verification flows is preferred.
  • Familiarity with SoC interconnect fabrics and their implications to HW acceleration IPs is preferred.
  • Strong communication skills and ability to work across various groups.


As a modeling architect, you will work with other HW architects to create accurate performance models to inform architectural decisions for the next-generation Neural Engine. In addition, you may work on prototyping software frameworks (such as compilers) for mapping and optimizing DNN workloads on the Neural Engine. Cross functional collaboration with HW design/verification teams as well as SW teams is an important part of this role. Excellent programming skills in C++ and Python is required.

Education & Experience

M.S. in CS/EE or related fields with at least 3+ years of relevant experience or B.S. with 5+ years of experience.


See job description


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