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 Signoff Lead - STA - Austin, Texas, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Other
Computers - Platforms
Computers - Networks
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200316062 / Latpro-3844496 
Date posted: Nov-30-2021
State, Zip: Texas, 78729

Description

Signoff Lead - STA

Austin , Texas , United States

Hardware

Summary

Posted: Nov 30, 2021

Role Number: 200316062

As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. The Signoff Engineer ensures that all critical, necessary and appropriate verification and analysis work has been performed on a design before tapeout. In this high-visibility position you will be responsible for the definition, development, and implementation of signoff requirements for PNR construction flows, and analysis for STA, Noise, and Clocks of high-volume state-of-the-art SOC, working with other teams in the organization to verify that the EDA flows and tools are set up and run correctly during the project, and all signoff criteria are met at the end of the project. This role also requires direct interaction with technology, CAD, and design groups to provide frontline support for enablement, enhancement, and debug requests.

Key Qualifications

  • The ideal candidate will have:
  • Knowledge of STA and Noise analysis flows and tools
  • Experience in timing closure, clock tree construction, and signal integrity
  • Experience with tools such as Primetime and Tempus
  • Spice simulation for path analysis and tools correlation
  • Preferably having experience in synthesis, floor planning, placement, and routing
  • Working knowledge of Physical Design construction tools such as ICC or EDI
  • Proficient in programming using Python, Perl and Tcl

Description

- Determine signoff criteria for STA, Signal Integrity, and Clock construction / simulation - Work with Integration, DFT, CAD, Tech, Power, and PNR teams - Participate in technology and design reviews for options of assessing critical timing interfaces - Develop and maintain signoff checks - Develop and maintain scripts for signoff verification - Resolve signoff timing requirements across all modes and corners - Verification of CAD flows - Drive signoff reviews with design teams - Enable design teams for signoff - Milestone and signoff scheduling. Signature delegation and tracking - Ability to work in a demanding, team-oriented environment - Support and debug signoff flow issues

Education & Experience

Bachelor's / Master's degree in EE with 7+ years of experience



Requirements

See job description

 

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